This invention relates to CMOS devices and fabrication processes and, in particular, to a process for forming state-of-the-art high performance silicon gate CMOS integrated circuits using a second polycrystalline silicon layer to provide enhanced metal-to-diffusion and metal-to-first layer polysilicon contacts.
The topographical and material properties of contact formation in MOSFET integrated circuits make this operation one of the most critical ones in the fabrication sequence. Contacts between two conductive materials, such as a metal and an underlying diffusion or polycrystalline silicon layer (also termed "poly" or "polysilicon") involve forming deep, steep-walled openings in an interlayer dielectric separating the two conductive layers. Aluminum contacts to diffusions often suffer from two problems: (1) metal spiking through the diffused junction, causing a short; and (2) metal necking or thinning at structural steps, causing increased susceptibility to electromigration-induced failure.
A consideration common to all contacts is the necessity for controlling the size and location with respect to the feature being contacted. Misalignment or oversizing causes short circuits with adjacent features. This possibility causes design rules to be expanded in order to avoid the nearby feature. Consequently, as overall circuit design rules shrink, minimum contact geometries and spacings can dominate other factors and determine the lower limit on device/cell sizes.
Additional problems arise in current, state-of-the-art processes in which the channel lengths typically are 3 microns or less and in which the source and drain junction depths are dimensionally very shallow (perhaps 0.3 micron) and the concentration of dopant such as arsenic, phosphorus or boron is low (approximately 1.times.10.sup.20 /cm.sup.3 or less). Nonetheless, this concentration in short channel devices may result in high field effects such as punch-through and hot electron injection. Lowering the concentration to reduce or minimize such high field effects increases the contact resistance and may increase the tendency for metal spiking.
Each of these problems (spiking, electromigration instability and high field effects) has been addressed in various ways in different types of processes. Many manufacturing processes for n-channel MOSFET integrated circuits (NMOS, HMOS, XMOS, etc.) utilize "enhanced contact diffusion" or "ECD". This is an extra diffusion sequence in which an impurity such as phosphorus is diffused into the contact regions of the integrated circuit (after formation of the n-type source and drain) and after the formation of contact windows in the interlayer oxide to the source/drain. This diffusion increases the n.sup.+ junction depth and concentration locally under the subsequently-formed metal contacts. This permits the use of relatively low concentrations of source/drain dopant to minimize high field effects, at the same time reduces the incidence of metal spiking through the shallow, n.sup.+ junctions in the MOSFET devices, and decreases the contact resistance, with little increase in process complexity.
In another process (POSA), both metal spiking and contact alignment in NMOS integrated circuits are improved. See Hsia et al, "Polysilicon Oxidation Self-Aligned MOS (POSA MOS)-A New Self-Aligned Double Source/Drain Ion Implantation Technique for VLSI", IEEE Electron Device Letters, Vol. EDL-3, No. 2, pp. 40-42, February 1982. After forming a phosphorus-doped polysilicon gate and forming n.sup.- phosphorus source/drain regions, the rapid oxidation rate of the heavily-doped n.sup.+ polysilicon relative to the lightly- doped n.sup.- source/drain regions is used to form an implant mask displaced from and at the edge of the gate. The device is then given a "blanket" implant to provide a heavily doped n.sup.+, self-aligned, locally enhanced contact diffusion. The polysilicon oxidation self-aligned structure (POSA) provides several structural and operational improvements in addition to self-aligned ECDs, including increased circuit density.
The criticality of contact alignment to NMOS integrated circuit devices is reduced in a fabrication approach described by Sakamoto et al. in "A New Self-Aligned Contact Technology", Proceedings of The International Solid State Circuits Conference, pp. 136-39, February 1980. These investigators use differential oxidation of doped polysilicon gates to selectively form a high quality interlevel oxide over the gates. Large, doped polysilicon contact pads are then formed around the n.sup.+ regions prior to deposition of a second interlayer dielectric of phosphorus-silicate glass (PSG). Using this self-aligned ECD approach, alignment of the contact cuts through the PSG is not critical because the polysilicon contact pads overlap both the gate and the active area edge. Presumably, the source and drain area of the MOSFETs is decreased and the density of exemplary MOS dynamic random access memory (DRAM) cells is increased. However, the improvements are realized at the expense of increased parasitic capacitances, which would be expected to limit the usefulness of the technique.
State-of-the-art high performance bipolar junction transistors are described by Graul et al., "High-Performance Transistors with Arsenic-Implanted Polysil Emitters", IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 4, August 1976, pp. 491-95. A primary feature of the fabrication process described by Graul et al. is the formation of the base by a single implantation with boron ions, followed by opening contact windows through a deposited oxide, depositing undoped polycrystalline silicon on the wafer, arsenic implanting the polysilicon, and then diffusing the arsenic into the base region to form a shallow emitter and a narrow base width. The advantages of the process, vis a vis conventional double-implanted transistors, include lower incidence of junction defects, higher emitter efficiency, self alignment of emitter contacts, and improved emitter-base junction breakdown. The polysilicon "interlayer" physically separates the metal from the junction and thereby decreases the diffusion or spiking of metal through the junction. The polysilicon may be partially consumed in a metal alloy step to raise the concentration of silicon solute to the solubility limit without spiking.
The problem of aluminum interconnect continuity over steps has been reduced by the application of a polysilicon underlayer beneath the aluminum metallization. However, the importance of maintaining a saturation percentage of silicon in the as-deposited aluminum has been reported by Vaidya who pointed out that such a two-layer Al/poly-si metallization will suffer from electromigration instability if the aluminum is pure. See Vaidya, "AL/Poly-Si Metallization For Small Geometry, Shallow Junction Contacts and Fine Line Interconnects", Abstract No. 228, Electrochemical Society Extended Abstracts, Spring Meeting, Montreal, Canada, May 9-14, 1982; and "Electromigration in Aluminum/Polysilicon Composites", Applied Physics Letters, Vol. 39, No. 11, pp. 900-902, December 1981.
An added benefit is obtained from the use of a doped polysilicon interlayer in contact regions, as reported by Jiang et al. in "A New Type of Bipolar Logic With Polysilicon Emitter Regions", Electronic Science and Technology Journal (Chinese), No. 7, pp. 7-12, 1980. Jiang et al. report the formation of bipolar junction transistors (BJTs) using doped polysilicon emitter regions (PER) involving a high quality planar junction between the doped poly and diffused substrate regions having opposite doping types. The implication of this type of junction for a polysilicon contact interlayer is that the contact will only be made to a region of doping which is the same as the doping in the polysilicon. Any adjacent feature which would be junction isolated in the substrate would also be junction isolated from the polysilicon contact. The main advantage of this characteristic would come from the ability to neglect the effects of partial contact misalignment and overetch at small junction isolated features. This would permit the implementation of design rules allowing tighter geometries, and would permit the formation of contact windows as large as, or even overlapping the active areas.
The use of enhanced n.sup.+ contact technology duallayer aluminum/polysilicon metalization in CMOS circuits and combined CMOS/bipolar circuits is described in copending NCR U.S. patent application Ser. No. 391,068 filed June 22, 1982 in the name of Paul Sullivan.
Despite the above-described benefits of enhanced metal-to-diffusion contacts for n.sup.+ contacts or p.sup.+ contacts in MOS integrated circuits, ECD technology has not, to the knowledge of this inventor, been previously used for both p.sup.+ contacts and n.sup.+ contacts in CMOS integrated circuits. Since CMOS processes involve both NMOS and PMOS transistors, the ECD should be applied to the contacts to both n.sup.+ and p.sup.+ regions, such as source/drain regions. CMOS processes cannot merely employ a blanket implant and diffusion to produce the enhancement as can be done in NMOS. By standard processing, ECD must be implemented by separately masking and implanting the n.sup.+ and the p.sup.+ contact regions to increase the doping and the junction depth in both types of contacts. This requirement of two additional photomasking steps is not economically justifiable, particularly in large volume manufacturing. Consequently, in order to provide both low contact resistance and to reduce the incidence of spiking, many CMOS processes simply use higher than nominal source/drain doping concentrations and deeper than nominal junction depths.
An additional complicating factor occurs in forming enhanced p.sup.+ contacts in PMOS structures. In the absence of a poly interlayer, the high diffusivity of boron requires the use of complex processing to produce an adequately-protected junction under the contact and still maintain minimum lateral p.sup.+ diffusion. In PMOS, enhanced p.sup.+ contacts have been achieved for small devices in an exemplary process by using a triple boron implant at three different energies. See Fichtner et al., "Experimental Results in Submicron-Size p-Channel MOSFET's", IEEE Electron Device Letters, Vol. EDL-3, No. 2, February 1982, pp. 34-37.